A static random access memory (SRAM) bitcell includes a pair of cross-coupled inverters. Depending upon the binary state of a stored data bit, a p-type metal oxide semiconductor (PMOS) transistor in one of the cross-coupled inverters may charge a true (Q) data node. Similarly, a PMOS transistor in a remaining one of the cross-coupled inverters may charge a complement (QB) data node depending the binary state of the stored data bit. The Q data node couples through a first n-type metal oxide semiconductor (NMOS) access transistor to a bit line whereas the QB data node couples through a second NMOS access transistor to a complement bit line. During a write operation in which the binary content of the bitcell is changed, one of the PMOS transistors will initially be on and charging its data node while the corresponding access transistor is attempting to discharge the same data node through the corresponding grounded bit or complement bit line. The NMOS access transistor must thus be relatively strong with regard to the PMOS transistor so that the data node can be discharged relatively quickly. To provide this strength, the NMOS access transistors may be relatively large as compared to the inverter PMOS transistors. But increasing the size of the NMOS access transistors reduces density for the resulting SRAM.
To strengthen the NMOS access transistor without such a loss in density, it is thus conventional to provide a negative boost voltage on the otherwise-grounded bit line during the write operation. This negative boost voltage applied during a write assist period increases the strength of the NMOS access transistor in comparison to the inverter PMOS transistor so that the NMOS access transistor can quickly discharge the corresponding data node yet each NMOS access transistor may remain relatively small to enhance density. The negative boost voltage is applied during the write assist period by coupling the appropriate bit line to a charged boost capacitor. But the charge on the boost capacitor is partially discharged during the write assist period through the write driver.
This discharge of the boost capacitor charge will now be further discussed with regard to a conventional memory 100 shown in FIG. 1. A write driver includes an inverter 115 in series with an inverter 105. An output of inverter 105 drives a true bit line selected through a column multiplexer 145 such as a true bit B1 or a true bit line B2 whereas the input data signal (data) drives an input of inverter 115. Inverter 105 includes a p-type metal oxide semiconductor (PMOS) transistor P1 having a source connected to a power supply voltage node supplying a power supply voltage VDD. A drain of transistor P1 connects to a drain of an n-type metal oxide semiconductor (NMOS) transistor M1. The drain nodes for transistors P1 and M1 (the output node for the data path through inverter 105) are coupled to column multiplexer 145. Similarly, the gates of transistors P1 and M1 from the input node for inverter 105 and are thus connected to the output of inverter 115. The source of transistor M1 connects to ground through an NMOS write assist transistor M3. An inverter 125 inverts a boost enable signal (boost_enb) to drive the gate of write assist transistor M3. In memory 100, the boost enable signal is active high such that it is a binary low value (ground) outside of the write assist period. Prior to the initiation of the write assist period, write assist transistor M3 is thus switched on. Should the input data signal have a binary high value, transistor M1 is also switched on such that the bit line is discharged to ground through transistor M1 and write assist transistor M3.
The output of inverter 125 is delayed through a pair of inverters 130 and 135 in series with inverter 125 to drive an anode of a boost capacitor 140 such as formed by the gate capacitance of a PMOS boost capacitor transistor P3 (both the drain and the source of boost capacitor transistor P3 are connected to the output of inverter 135 to form the anode of boost capacitor 140). The gate of boost capacitor transistor P3 forms the cathode of boost capacitor 140. Prior to the initiation of the write assist period, the anode of boost capacitor 140 is charged to the power supply voltage VDD whereas the cathode of boost capacitor 140 is discharged to ground. The assertion (note that as used herein, a signal is deemed to be “asserted” if it is charged high in the case of an active-high signal or discharged in the case of an active-low signal) of the boost enable signal at the initiation of the write assist period is delayed through the pair of inverters 130 and 135 to discharge the anode of boost capacitor 140. The gate capacitance for boost capacitor transistor P3 then pulls its gate voltage below ground to provide a negative write assist voltage boost to the selected bit line.
To drive a selected complementary bit line, the write driver also includes an inverter 120 in series with an inverter 110. Inverter 120 inverts a complement data bit (data_bar) to drive the input of inverter 110, which is formed by a PMOS transistor P2 in series with an NMOS transistor M2. The data path output of inverter 110 (the drains of transistors P2 and M2) drives the selected complement bit line though column multiplexer 145. When the data bit is false, the complement data bit is of course true such that transistor P2 is on and transistor M2 off prior to the write assist period. In particular, the gate of transistor M2 is grounded by the output of inverter 120 when the complement data bit is true. During the write assist period, the source voltage of transistor M2 is then pulled below ground by, for example, as much as half a volt. The gate to source voltage for transistor M2 is thus positive despite the grounding of its gate such that the boost charge from boost capacitor 140 is discharged through transistor P2 into the power supply node at its source and also into the complement bit line. An analogous discharge through transistor M1 occurs during the write assist period should the data bit input signal be a binary high value. This discharge of the boost charge not only wastes power but also weakens the negative boost for the discharged bit line.
Column multiplexer 145 suffers from an analogous discharge of the boost charge. For example, column multiplexer 145 may select for a first bit line pair (true bit line B1 and a complement bit line B1) through an NMOS column multiplexer transistor M4 and an NMOS column multiplexer transistor M5, respectively. An column multiplexer control signal wm0 controls the gates of column multiplexer transistors M4 and M5 to switch these transistors on to couple the output of write driver inverter 105 to the true bit line B1 and to couple the output of write driver inverter 110 to the complement bit line B1. Similarly, column multiplexer 145 may select for a second bit line pair (true bit line B2 and complement bit line B2) through an NMOS column multiplexer transistor M6 and an NMOS column multiplexer transistor M7, respectively. These column multiplexer transistors are switched on through the assertion of a column multiplexer control signal wm1. If the first bit line pair is selected by column multiplexer 145, column multiplexer control signal wm1 is de-asserted such that column multiplexer transistors M6 and M7 are both off. Should the data bit driving the input of write driver inverter 115 be false, transistor M1 in write driver inverter 105 will be switched on such that the negative boost from boost capacitor 140 conducts though transistor M1 during the write assist period to pull the drains of write multiplexer transistors M4 and M6 to the negative boost voltage. Although column multiplexer transistor M6 has its gate grounded, it will still be weakly on due to the positive gate-to-source voltage that it receives from the negative boost during the write assist period. Column multiplexer transistor M6 will thus leak boost charge during the write assist period into the unselected true bit line B2. More generally, a column multiplexer transistor corresponding to an unselected bit line column multiplexer 145 will leak charge in this fashion in every write assist period.
Accordingly, there is a need in the art for memories having an enhanced negative bit line boost with reduced power consumption.